Quantizer for a sigma delta modulator

ABSTRACT

A quantizer for a sigma delta modulator comprising at least one preliminary stage V 1 , V 2 ), the quantizer quantizing an input signal (E Q ) present at it in accordance with at least one threshold signal (y th,i ) and outputting it as a result value (y Q ) at a digital result output (OUT), wherein the quantizer has a number of comparators ( 5   j ) corresponding to the number of threshold signals (y th,j ), which compare the input signal (E Q ) with the respective threshold signal (y th,j ) , the threshold signal being reduced or increased by a correction voltage (y dac3 ) or a correction current, the correction voltage or correction current being generated in accordance with the result value (y Q ) output at the result output (OUT).

[0001] The invention relates to a quantizer for a sigma delta modulator according to the preamble of Patent claim 1.

[0002] In recent years, sigma delta modulation has gained increasing significance in the field of analog/digital (A/D) and digital/analog (D/A) conversion. This is mainly attributable to the low requirements for the analog components of signal converters. Digital circuits are gaining more and more significance in present day signal processing. To be able to convert the signals from the analog environment and then to be able to process them digitally, A/D converters are necessary. It is desirable to integrate converters and the remaining digital circuit on a single chip. Since the digital proportion in most cases dominates the chip area, it also determines the circuit technology. However, digital process technologies make it difficult to produce precise analog integrated circuit components in which very high accuracies and little manufacturing variation are demanded. This is where the simplicity and ruggedness of analog components of the sigma delta modulators become important, which predestine the sigma delta converters for implementations in, for example, digital VLSI technology.

[0003] A further advantage of the sigma delta modulators lies in the fact that they need less current than the conventional A/D converters, which also qualifies them in the important field of portable receivers. Similarly, they are distinguished by a higher signal bandwidth, which makes them interesting for application in xDSL transceiver technology.

[0004] The problem with sigma delta modulators is that errors occur due to propagation delays in the individual components (excess loop delay), especially toward higher frequencies to be converted, which limits their application to high frequencies (>1 GHz). With regard to the problems of excess loop delays, see also J. A. Cherry, W. M. Snelgrove, Continuous-Time Delta Sigma Modulator for High Speed A/D Conversion, Kluwer Academic Publishers 2000, pages 75-103.

[0005] A known approach to compensate for these errors induced by delay differences is the approach, known from P. Benabes, M. Keramat, R. Kielbasa, A methodology for designing continuous-time sigma-delta modulators, IEEE European Design and Test Conference 1997, pages 45-50, of introducing an additional feedback circuit (inner loop) which is formed by an additional adder between the quantizer and the last integrator preceding it.

[0006]FIG. 1 shows a conventional continuous-time second order sigma delta modulator with two preliminary stages V₁ and V₂ and with correction means. The signal x to be converted, which is present at the input IN, is supplied to the quantizer 2 at its input E_(Q) via two integrators 4 ₁ and 4 ₂, each of which is in each case preceded by an adder 3 ₁ and 3 ₂, respectively, to link up with the feedback signal. Before that, however, the signal to be quantized is again combined with the feedback signal via the adder 10. This takes into consideration and compensates for the influence of the delay in the individual components.

[0007]FIG. 2 shows a possible conversion of such a concept known from W. Redman-White, A. M. Durham, A fourth order Converter with self-tuning Continuous Time Noise Shaper, from Proceedings of ESSCIRC 1991, pages 249-252.

[0008] In this concept, current AD converters 61 to 62 are used as digital/analog converters for the feedback signal R_(i), the integrators 4 ₁ and 4 ₂ nbeing formed by operational amplifiers and the compensation adder 10 also being constructed by an operational amplifier preceded by a current AD converter 6 ₃. In this solution, the summing nodes 3 _(i) are formed by the inputs of the operational amplifiers. The summing signals are the currents which flow through the input resistors and into the current generators in the respective feedback circuit.

[0009]FIG. 3 shows a diagram of a three-bit resolution sigma delta modulator constructed in this way in which seven threshold voltages are used.

[0010] According to the arrangement specified above, the sum is formed with the feedback signal before the quantizer. The comparators i=1 to N of the quantizer, therefore, must perform the weighting

(V ₂ −V _(daC3))>V _(th,i)

[0011] (see also FIG. 4) where V₂ is the amount of the intermediate signal y₂ after the second integrator 4 ₂.

[0012] The disadvantageous factor in this arrangement and procedure is, however, that a highly accurate active element (additional adder) must be provided in the signal path, with all the problems with regard to manufacturing methods and steps, layout design and waste in the manufacturing, and that the current consumption is considerably increased by this, which limits the fields of application especially in the case of portable applications which require current saving.

[0013] It is, therefore, the object of the invention to provide a sigma delta modulator with a quantizer in which the delays are compensated for by the individual components but no additional element is provided in the signal path.

[0014] This object is achieved by a quantizer having the features specified in claim 1.

[0015] According to the invention, it is provided that the quantizer exhibits comparators in accordance with the number of threshold voltages, which compare the input signal with the respective threshold voltage, the threshold voltage being reduced or increased by a correction voltage which is generated in accordance with the result value output at the result output.

[0016] The invention proposes to adapt the threshold voltages for the comparators in the quantizer and no longer to adapt the signal to be quantized in the signal path before the quantizer as previously. This makes it possible to considerably simplify the design of the semiconductor circuit which also is no longer so critical in its manufacture since tolerances can be wider in this case than in the case of active analog elements directly in the signal path. The additional adder is dispensed with. The threshold voltage can be adapted over an entire clock cycle which is sufficient time. The entire system is more stable and, in addition, no longer produces so many delay errors since an active element has been removed from the signal path. This also reduces the current consumption of the sigma delta modulator and it can be implemented with less space required on a chip. In addition, higher sampling rates can be achieved since the sampling rate is increased due to the reduction in the delay errors. Applications in the XDSL field with the high sampling rates can be achieved more easily and the field of use of the sigma delta modulators is greater than was hitherto conceivable.

[0017] A preferred embodiment of the invention provides that a digital/analog converter is provided which generates an analog rough signal from the digital result value. This makes it possible to supply the individual adders in a simple manner with a feedback signal weighted with a factor.

[0018] Preferably, the rough signal is in each case multiplied by a predetermined factor to the respective feedback signal of a preliminary stage corresponding to the position and the number of preliminary stages in the signal path.

[0019] The correction voltage is advantageously a voltage corresponding to the result value multiplied by a fixed factor.

[0020] One embodiment of the invention provides that the factor is a simple fraction.

[0021] A preferred embodiment of the invention provides that a digital adder is provided which adds the factor to the result value and connects a previously generated threshold voltage, corresponding to the result, to the comparators.

[0022] A digital/analog converter is advantageously provided which generates the voltage corresponding to the result value.

[0023] According to an especially preferred embodiment of the invention, it is provided that the sigma delta modulator is of second order with two preliminary stages.

[0024] The sigma delta modulator is advantageously and, therefore, preferably a continuous-time sigma delta modulator.

[0025] Means for editing the output signals of the adder are preferably provided.

[0026] Advantageously, a number of comparators corresponding to the resolution of the quantizer is provided, the comparators exhibiting uniformly graduated threshold voltages.

[0027] Accordingly, it is provided, in accordance with one embodiment of the invention, that a reference voltage generator is provided which supplies part voltages from which the threshold voltages are generated.

[0028] Further advantages, special features and suitable developments of the invention are obtained from the further subclaims or their subcombinations.

[0029] In the text which follows, the invention will be explained in further details with reference to the drawing, in which:

[0030]FIG. 1 shows a continuous-time sigma delta modulator according to the prior art,

[0031]FIG. 2 shows an actual embodiment of the continuous-time sigma delta modulator from FIG. 1,

[0032]FIG. 3 shows a schematic diagram of the quantizing steps via the analog input voltage,

[0033]FIG. 4 shows a section from FIG. 1, the signals being shown clearly,

[0034]FIG. 5 diagrammatically shows a quantizer according to the invention with the individual signals corresponding to the section from FIG. 4,

[0035]FIG. 6 shows a continuous-time sigma delta modulator according to the invention, and

[0036]FIG. 7 shows a diagrammatic representation of a more specific configuration of a quantizer according to the invention.

[0037] Identical reference symbols in the figures designate identical or identically acting elements.

[0038]FIG. 5 clearly shows the difference from previously known approaches (see also FIG. 4). The comparators i=1 to N of the quantizers no longer need to perform the weighting

(V _(Input) −V _(dac3))>V _(th,i)

[0039] but

V _(Input) >V _(th,i) ÷V _(dac3).

[0040] Accordingly, there is no longer any need to shift the signal in the signal path before the comparators.

[0041] Which each clock cycle any comparator of the quantizer receives an adapted threshold voltage

Y′ _(th,i) =Y _(th,i) +Y _(dac3) (t)

[0042] The ramp voltage drawn as a continous line shows the adapted voltage. With a 3 bit quantizer eight shifted ramps should be drawn but have been omitted for sake of clarity.

[0043] The new principle is the summation of the feedback signal with the threshold voltages of the comparators.

[0044] A noncritical adaptation of the threshold voltages of the comparators in the quantizer is adequate. It is not necessary to convert the digital result y_(Q) into a separate analog voltage. The values can be simply digitally added, followed by a corresponding connection of a reference voltage (see also FIG. 7).

[0045]FIG. 6 shows the approach according to the invention.

[0046] Specifically, the threshold voltages y_(th,i) can be summed with the correction voltage y_(dac3) (=b3*y_(Q)) in a very simple manner since the factor b₃ is in most cases a simple fraction (for example ½, ¾, etc.). As a result, the threshold voltage y_(th,i) can be fast and dynamic without having to intervene in the familiar and proven structures of the circuits supplying the threshold voltages. This applies both to the digital area and to the analog area, also including current or voltage reference.

[0047] The approach according to the invention no longer has any fixed threshold voltages y_(th,i) but adapts them in each case by the current correction voltage y_(dac3)=b3*y_(Q).

[0048] [lacuna] drawn ramp voltage is to illustrate the adapted voltage. In the case of a three-bit quantizer, eight shifted ramps should actually be drawn but were omitted in order to retain clarity.

[0049] The new principle is the summation of the feedback signal with the threshold voltages of the comparators.

[0050] A noncritical adaptation of the threshold voltages of the comparators in the quantizer is adequate. It is not necessary to convert the digital result y_(Q) into a separate analog voltage. The values can be simply digitally added, followed by a corresponding connection of a reference voltage (see also FIG. 7).

[0051]FIG. 6 shows the approach according to the invention.

[0052] Specifically, the threshold voltages y_(th,i) can be summed with the correction voltage y_(dac3) (=b3*y_(Q)) in a very simple manner since the factor b₃ is in most cases a simple fraction (for example ½, ¾, etc.) . As a result, the threshold voltage y_(th,i) can be fast and dynamic without having to intervene in the familiar and proven structures of the circuits supplying the threshold voltages. This applies both to the digital area and to the analog area, also including current or voltage reference.

[0053] The approach according to the invention no longer has any fixed threshold voltages y_(th,i) but adapts them in each case by the current correction voltage y_(dac3)=b3*y_(Q).

[0054]FIG. 7 diagrammatically shows an implementation of a preferred embodiment of the quantizer 2 for a sigma delta modulator 1 with b₃={fraction (1/2 )} and eight thresholds, in which the addition of the feedback value IN_DAC<0:6> is already performed in the purely digital domain. This does not require a digital/analog converter. The part reference voltages x * Vref are generated, for example, by a chain of resistors.

[0055] A digital adder 66 is provided which adds the digital result value IN_DAC<0:6> to the last weighting of the comparators 61 of the quantizer to the threshold signal voltages by increasing or reducing the threshold signal voltages 63 _(i) by steps corresponding to the digital result value. For this purpose, switches 67 are opened or closed correspondingly.

[0056] The adaptation to the delay differences by means of the factor b₃ can take place in the adder 66 itself which, in accordance with the result of the addition with the feedback value IN_DAC<0:6> (result of the previous weighting of the quantizer), connects the corresponding threshold voltages Vth_(i) by means of the switches 67 to the individual inputs of the comparators 61 which then carry out the weighting with the input signal 62 (IN) to the respective result bit Qi.

[0057] The quantizer 2 has a number of comparators 61 corresponding to the number of its resolution intervals.

[0058] The comparators 61 compare the input signal voltage 62 (IN) with in each case their threshold signal voltage 63 _(i) and, if the input signal exceeds or drops below the threshold signal, a corresponding digital result bit (0/1) (Qi) is output.

[0059] To generate the various threshold signal voltages 63 _(i), a reference voltage generator 65 is provided which supplies a separate threshold signal voltage 63 _(i) to each voltage comparator 61 via the switches 67 in accordance with the output data Add<0:6> of the adder 66. The differences of the individual threshold signal voltages 63 _(i) remains the same but, in accordance with the result Add<0:6> of the adder 66, the voltage level of each threshold signal voltage 63 _(i) is increased or lowered in accordance with the result IN_DAC<0:6> of the previous weighting of the quantizer.

[0060] In accordance with the result of the summation, therefore, part voltages {fraction (1/14)}*Vref, {fraction (2/14)}*Vref, . . . are added to the threshold voltage V_(th) by opening and closing switches and are connected to the comparators 61. In the example shown and in the text which follows, a 3-bit quantizer with seven steps is shown in which b₃=½ is selected. However, other values and resolutions can also be implemented depending on the application.

[0061] The seven threshold voltages of the comparators are, therefore, no longer fixed with respect to Vref and to the previously fixed basic voltages (with respect to Vref)

+{fraction (12/14)}, +{fraction (8/14)}, +{fraction (4/14)}, 0, −{fraction (4/14)}, −{fraction (8/14)}, −{fraction (12/14)}

[0062] One of the following values is added to all threshold voltages with each clock cycle in accordance with the actual and current value of the result value from the digital adder 66:

+{fraction (7/14)}, +{fraction (5/14)}, +{fraction (3/14)}, +{fraction (1/14)}, −{fraction (1/14)}, −{fraction (3/14)}, −{fraction (5/14)}, −{fraction (7/14)}

[0063] The resultant seven signals are compared with the current input signal, to be weighted, of the quantizer by the comparators as a result of which the next digital result is generated.

[0064] The arrangement of the comparators and the comparators themselves can also be formed symmetrically with a positive and a negative signal path.

List of Reference Symbols

[0065]1 Sigma delta modulator

[0066]2 Quantizer

[0067]3 _(i) Adder

[0068]4 _(i) Integrator

[0069]5 _(i) 61 Comparators

[0070]6 Digital/analog converter

[0071]7,66 Digital adders

[0072]8 Amplifier

[0073]9 Reference voltage generator

[0074]10 Compensation adder

[0075]11 Multiplier

[0076]62 Input signal

[0077]63 _(i) Threshold signal voltage

[0078]67 Voltage switch

[0079] IN Signal input

[0080] OUT Result output

[0081] x Evaluation signal

[0082] y_(Q) Result value

[0083] y₁,y₂ Intermediate signals

[0084] EQ Input signal

[0085] y_(th,i), 63 _(i) Threshold voltage

[0086] y_(dac3) Correction voltage

[0087] V_(i) Preliminary stage

[0088] E_(i) Preliminary stage input signal

[0089] A_(i) Preliminary stage output signal

[0090] R_(i) Feedback signal

[0091] RS Rough signal

[0092] b₃ Factor

[0093] Qi Result bit 

1. A quantizer (2) for a sigma delta modulator (1) comprising at least one preliminary stage (V1, V2), the quantizer (2) quantizing an input signal (E_(Q)) present at it in accordance with at least one threshold signal (y_(th,i)) and outputting it as a result value (y_(Q)) at a digital result output (OUT), wherein the quantizer (2) has a number of comparators (5 _(j)) corresponding to the number (j) of threshold signals (y_(th,j)), which compare the input signal (E_(Q)) with the respective threshold signal (y_(th,j)), the threshold signal being reduced or increased by a correction voltage (y_(dac3)) or a correction current, the correction voltage or correction current being generated in accordance with the result value (y_(Q)) output at the result output (OUT).
 2. The quantizer as claimed in claim 1, wherein a number of comparators (5i, 6L) corresponding to the resolution of the quantizer (2) is provided, the comparators having uniformly graduated threshold voltages (Vth,i) or threshold currents.
 3. The quantizer as claimed in claim 2, wherein the quantizer (2) has a number of voltage comparators (61) corresponding to the number of its resolution intervals, the voltage comparators comparing the input signal (21) present as input signal voltage (62) with an associated threshold signal voltage (63 _(i)) and, if the input signal voltage exceeds or drops below the threshold signal voltage, outputting a corresponding digital result bit (0/1) (Qi), a digital adder (66) being provided which adds the digital result value (22) of the last weighting of the comparators of the quantizer (1) to the individual threshold signal voltages of the comparators by increasing or reducing the threshold signal voltages by part voltages (25) corresponding to the digital result value.
 4. The quantizer as claimed in claim 3, wherein a reference voltage generator (65) is provided which generates the threshold signal voltages (63 _(i)), which are different for each voltage comparator (61), the threshold signal voltages being selectable in part voltages (25), the threshold signals exhibiting, in particular, fixed differences with respect to one another.
 5. The quantizer as claimed in one of claims 1 to 16, wherein the adder (66) is associated with a switching mechanism which has switches (67) at the inputs of which the part voltages (25) of the reference voltage generator (65) are present and the outputs of which are connected to the inputs (Vth_(i)) for the threshold signal voltages (63 _(i)) of the comparators (61), the switches being controlled by the output signal (Add<0:6>) of the adder.
 6. A sigma delta modulator (1) comprising a quantizer (2) as claimed in one of claims 1 to
 5. 7. A sigma delta modulator (1) comprising a signal input (IN) at which an evaluation signal (x) to be evaluated is present, and a digital result output (OUT) which outputs a digital result value (y_(Q)), a quantizer (2) being provided which quantizes an input signal (E_(Q)) present at it in accordance with at least one threshold voltage (y_(th,i)) and outputs it as a result value (y_(Q)) at the digital result output (OUT), the quantizer (2) being preceded at its input by at least one preliminary stage (Vi), which comprises an adder (3 _(i)), processing a preliminary stage input signal (E_(i)) with an integrator (4 _(i)) following the adder in the signal path and supplying a preliminary stage output signal (A_(i)), the adder (3 _(i)) being supplied with a feedback signal (R_(i)), generated in dependence on the result value (y_(Q)) for addition to the preliminary stage input signal (E_(i)), the evaluation signal (x) being present as preliminary stage input signal (E₁) at a first preliminary stage (V₁) and the preliminary stage output signal (A_(n−1)) of the in each case previous preliminary stage (V_(n−)) in the signal path being present as preliminary stage input signal (E_(n)) at each further preliminary stage (V_(n)), the last preliminary stage (V_(m)) before the quantizer (2) supplying the input signal (E_(Q)) to the quantizer as preliminary stage output signal (A_(m)), wherein the quantizer (2) exhibits a number of comparators (5 _(j)) corresponding to the number (j) of threshold voltages (y_(th,j)), which compare the input signal (E_(Q)) with the respective threshold voltage (y_(th,j)), the threshold voltage being reduced or increased by a correction voltage (y_(dac3)), the correction voltage being generated in accordance with the result value (y_(Q)) output at the result output (OUT).
 8. The sigma delta modulator as claimed in claim 7, wherein a digital/analog converter (6) is provided which generates an analog rough signal (RS) from the digital result value (y_(Q)).
 9. The sigma delta modulator as claimed in claim 8, wherein the rough signal (RS) is in each case multiplied by a predetermined factor (b_(i)) to the respective feedback signal (R_(i)) of a preliminary stage (V_(i)) corresponding to the position (i) and the number of preliminary stages (V_(i)) in the signal path.
 10. The sigma delta modulator as claimed in one of claims 7 to 9, wherein the correction voltage (y_(dac3)) is a voltage corresponding to the result value (y_(Q)) multiplied by a fixed factor (b₃).
 11. The sigma delta modulator as claimed in claim 10, wherein the factor (b₃) is a simple fraction.
 12. The sigma delta modulator as claimed in one of the preceding claims, wherein a digital/analog converter (6) is provided which generates the voltage corresponding to the result value.
 13. The sigma delta modulator as claimed in one of the preceding claims, wherein a digital adder (7) is provided which adds the factor (b₃) to the result value (y_(Q)) and connects a previously generated threshold voltage (y_(th,i)), corresponding to the result, to the comparators (5 _(i)).
 14. The sigma delta modulator as claimed in one of the preceding claims, wherein the sigma delta modulator is of second order with two preliminary stages.
 15. The sigma delta modulator as claimed in one of the preceding claims, wherein the sigma delta modulator is a continuous-time sigma delta modulator.
 16. The sigma delta modulator as claimed in one of the preceding claims, wherein a device (8) for editing the output signals of the adder (3 _(i)) is provided.
 17. The sigma delta modulator as claimed in one of the preceding claims, wherein a number of comparators (5 _(i)) corresponding to the resolution of the quantizer (2) is provided, the comparators exhibiting uniformly graduated threshold voltages.
 18. The sigma delta modulator as claimed in one of the preceding claims, wherein a reference voltage generator (9) is provided which supplies part voltages, from which the threshold voltages (y_(th,i)) are generated. 